JOSÉ LUIS
AYALA RODRIGO
Catedrático de universidad
École Polytechnique Fédérale de Lausanne
Lausana, SuizaPublicaciones en colaboración con investigadores/as de École Polytechnique Fédérale de Lausanne (23)
2023
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HackRF + GNU Radio: A software-defined radio to teach communication theory
International Journal of Electrical Engineering and Education, Vol. 60, Núm. 1, pp. 23-40
2019
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Cyber-physical systems design methodology for the prediction of symptomatic events in chronic diseases
Complexity Challenges in Cyber Physical Systems: Using Modeling and Simulation (M&S) to Support Intelligence, Adaptation and Autonomy (wiley), pp. 223-253
2018
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Fast Energy Estimation Through Partial Execution of HPC Applications
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
2012
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Fast and scalable temperature-driven floorplan design in 3D MPSoCs
LATW 2012 - 13th IEEE Latin American Test Workshop
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Preface
IFIP Advances in Information and Communication Technology
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Through silicon via-based grid for thermal control in 3D chips
Design Technology for Heterogeneous Embedded Systems (Springer Netherlands), pp. 303-320
2011
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3D Thermal-aware floorplanner for many-core single-chip systems
LATW 2011 - 12th IEEE Latin-American Test Workshop
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Adaptive task migration policies for thermal control in MPSoCs
Lecture Notes in Electrical Engineering, Vol. 105 LNEE, pp. 83-115
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Thermal modeling and management of liquid-cooled 3D stacked architectures
IFIP Advances in Information and Communication Technology
2010
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Adaptive task migration policies for thermal control in MPSoCs
Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
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Energy efficiency using loop buffer based instruction memory organizations
Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
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Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal, Vol. 43, Núm. 4, pp. 327-341
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Thermal-aware compilation for register window-based embedded processors
IEEE Embedded Systems Letters, Vol. 2, Núm. 4, pp. 103-106
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Thermal-aware compilation for system-on-chip processing architectures
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
2009
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Dynamic thermal management in 3D multicore architectures
Proceedings -Design, Automation and Test in Europe, DATE
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Modeling and dynamic management of 3D multicore systems with liquid cooling
Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
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Thermal-aware data flow analysis
Proceedings - Design Automation Conference
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Through silicon via-based grid for thermal control in 3D chips
Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering
2008
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Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures
Integration, the VLSI Journal, Vol. 41, Núm. 1, pp. 38-48
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Register file reliability analysis through cycle-accurate thermal emulation
Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems