Publicaciones (5) Publicaciones de FELIPE SERRANO LÓPEZ

2018

  1. Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 fieldprogrammable gate array

    IET Computers and Digital Techniques, Vol. 12, Núm. 4, pp. 150-157

2016

  1. Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

    Neurocomputing, Vol. 171, pp. 1606-1609

  2. Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA

    Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

2015

  1. A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

    IEEE Transactions on Nuclear Science, Vol. 62, Núm. 4, pp. 1617-1624

2013

  1. A study of the robustness against SEUs of digital circuits implemented with FPGA DSPs

    Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS