Publicaciones en colaboración con investigadores/as de University of Rome Tor Vergata (20)

2017

  1. Onboard payload-data dimensionality reduction

    International Geoscience and Remote Sensing Symposium (IGARSS)

  2. Welcome from the general chair

    Simulation Series

2015

  1. A class of SEC-DED-DAEC codes derived from orthogonal Latin square codes

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 5, pp. 968-972

  2. A method to protect Bloom filters from soft errors

    Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

  3. A synergetic use of bloom filters for error detection and correction

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 3, pp. 584-587

  4. Low delay single symbol error correction codes based on reed solomon codes

    IEEE Transactions on Computers, Vol. 64, Núm. 5, pp. 1497-1501

2014

  1. A method to extend orthogonal latin square codes

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 7, pp. 1635-1639

  2. Efficient implementation of error correction codes in hash tables

    Microelectronics Reliability, Vol. 54, Núm. 1, pp. 338-340

  3. FastTag: A technique to protect cache tags against soft errors

    IEEE Transactions on Device and Materials Reliability, Vol. 14, Núm. 3, pp. 935-937

2013

  1. A method to construct low delay single error correction codes for protecting data bits only

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, Núm. 3, pp. 479-483

  2. An efficient technique to protect serial shift registers against soft errors

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, Núm. 8, pp. 512-516

  3. Concurrent error detection for orthogonal latin squares encoders and syndrome computation

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, Núm. 12, pp. 2334-2338

  4. Low complexity concurrent error detection for complex multiplication

    IEEE Transactions on Computers, Vol. 62, Núm. 9, pp. 1899-1903

  5. Optimised decoding of odd-weight single error correction double error detection codes with 64 bits

    Electronics Letters, Vol. 49, Núm. 25, pp. 1617-1618

  6. Reducing the cost of implementing error correction codes in content addressable memories

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, Núm. 7, pp. 432-436

  7. Reducing the cost of single error correction with parity sharing

    IEEE Transactions on Device and Materials Reliability, Vol. 13, Núm. 3, pp. 420-422

2012

  1. Area efficient concurrent error detection and correction for parallel filters

    Electronics Letters, Vol. 48, Núm. 20, pp. 1258-1260

  2. Low-cost single error correction multiple adjacent error correction codes

    Electronics Letters, Vol. 48, Núm. 23, pp. 1470-1472

2010

  1. A MDA-based approach for the development of DEVS/SOA simulations

    Spring Simulation Multiconference 2010, SpringSim'10

  2. A MDA-based approach for the development of DEVS/SOA simulations

    Simulation Series