Memory disambiguation hardwarea Review

  1. Castro, Fernando
  2. Chaver, Daniel
  3. Piñuel, Luis
  4. Prieto, Manuel
  5. Tirado Fernández, Francisco
Revista:
Journal of Computer Science and Technology

ISSN: 1666-6038

Año de publicación: 2008

Título del ejemplar: Twenty-Fourth Issue

Volumen: 8

Número: 3

Páginas: 132-138

Tipo: Artículo

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Otras publicaciones en: Journal of Computer Science and Technology

Resumen

One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.

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Fuente de los datos: Dialnet