A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

  1. Resano, J.
  2. Verkest, D.
  3. Mozos, D.
  4. Vernalde, S.
  5. Catthoor, F.
Revue:
Microprocessors and Microsystems

ISSN: 0141-9331

Année de publication: 2004

Volumen: 28

Número: 5-6 SPEC. ISS.

Pages: 291-301

Type: Article

DOI: 10.1016/J.MICPRO.2004.03.015 GOOGLE SCHOLAR
La source de données: Scopus