Multithreaded dense linear algebra on asymmetric multi-core processors

  1. Catalán Pallarés, Sandra
Supervised by:
  1. Enrique Salvador Quintana Ortí Director
  2. Rafael Rodriguez Sanchez Co-director

Defence university: Universitat Jaume I

Fecha de defensa: 06 February 2018

  1. Ramón Doallo Chair
  2. José Ignacio Aliaga Estellés Secretary
  3. Paolo Bientinesi Committee member

Type: Thesis

Teseo: 529338 DIALNET lock_openTDX editor


This dissertation targets two important problems. The first one is the design of low-level DLA kernels for architectures comprising two (or more) classes of cores. The main question we have to address here is how to attain a balanced distribution of the computational workload among the heterogeneous cores while taking into account that some of the resources, in particular cache levels, are either shared or private. The second question is partially related to the first one. Concretely, this dissertation explores an alternative to runtime-based systems in order to extract “sufficient" parallelism from complex DLA operations while making an efficient use of the cache hierarchy of the architecture. Thus, the main goal of this thesis is the study, design, development and analysis of experimental solutions that are architecture-aware for the execution of DLA operations on low power architectures, more specically asymmetric platforms.