Aportaciones al diseño de unidades de procesamiento de datos para aplicaciones espaciales mediante el empleo FPGAs

  1. GUZMÁN GARCÍA, DAVID
Supervised by:
  1. Manuel Prieto Mateo Director
  2. Óscar Rodríguez Polo Co-director

Defence university: Universidad de Alcalá

Fecha de defensa: 28 February 2012

Committee:
  1. Daniel Meziat Luna Chair
  2. Sebastián Sánchez Prieto Secretary
  3. Segundo Esteban San Román Committee member
  4. Ramón Puigjaner Trepat Committee member
  5. Fernando Aguado Agelet Committee member

Type: Thesis

Teseo: 330599 DIALNET lock_openTESEO editor

Abstract

This work describes the research done in the field of data processing units for space applications. Typically, these units are based on a microprocessor. Modern processors include features such as pipelines, caches, and branch predictors that result in notable performance improvements. However, these enhancing features introduce a high level of unpredictability and uncertainty into the workload behavior. In space applications, this fact takes on vital importance because these elements are designed to perform real time systems with critical tasks and subject to exhaustive analysis process prior to its acceptance. The main objective of this thesis has been to provide a number of improvements to the architecture of the LEON microprocessors family, which is the European Space Agency’s recommended platform for onboard data processing units. These improvements are focused to ameliorate the determinism of the system execution, thus to provide an observation capability in order to aid the extra-functional properties analysis of the system executed, worst case execution time, cache hit rate and coverage. In this mode the research work includes the introduction of a new module in the microprocessor in charge of collecting analysis information in non-intrusive mode, avoiding the interferences produced by other solutions which employ code instrumentation. Information includes data and instruction hit rates, number of performed instructions performed, clock cycles needed for their execution, branch instructions executed and a trace of the program execution based on the taken branch instructions. The second contribution is focused to increase the architecture determinism, includes a mechanism to avoid the jitter in task context switch and the latency due to interruptions, moreover reduces significatly the time needed in both mechanisms. A key aspect of this improvement is the fact that it can be used without modifying the compiler because it complies with the current set of instructions for the family, and only requires the adaptation of the real-time operating system. FPGA technology has been employed to support the research work. Nowadays, Field Programmable Gate Arrays (FPGAs) have been gaining popularity in space applications. Application Specific Integrated Circuit (ASIC) development costs in both economic and temporal terms have required new solutions, and it is at this point that FPGAs arise. Through FPGAs designers own a platform where is possible to integrate a complex digital system in only one chip, conserving power consumption, and reducing the number of components that are employed. Also, due to its versatility, it can modify and improve the components integrated in it, adapting designs to a specific scenario providing “ad-hoc“ solutions. The contributions made by this research work are found in the data processing unit design proposal, based on FPGAs and the LEON microprocessor as the main elements.