Arquitectura de decoficador de video orientada al bajo consumo para acompañantes móviles digitales
- Montoya Lince, Adrián
- Rivera Vélez, Fredy Alexander
ISSN: 0122-1701
Argitalpen urtea: 2009
Alea: 2
Zenbakia: 42
Orrialdeak: 369-374
Mota: Artikulua
Beste argitalpen batzuk: Scientia et Technica
Laburpena
This paper deals with the implementation onto an FPGA of a low power video decompression system that complies with the H.263 standard. Four different architectures for the 2D-IDCT module have been implemented, looking for the reduction of the decoder�s dynamic power consumption. Low power techniques employed in this work consist of bit-width reduction in MAC operations (low precision multipliers), avoiding block null processing, and memory bus commutation reduction. Results are very promising in terms of power consumption, saving up to 70% in the 2D-IDCT module, and up to 74% in the whole H.263 decoder.