Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

  1. Roberto Rodríguez-R
  2. Fernando Castro
  3. Daniel Chaver
  4. Luis Piñuel
  5. Francisco Tirado
Actas de las XXIV Jornadas de Paralelismo
  1. Guillermo Botella (coord.)
  2. Alberto A. Del Barrio (coord.)

Publisher: Limencop S.L.

ISBN: 978-84-695-8330-2

Year of publication: 2013

Pages: 18-23

Congress: Jornadas de Paralelismo (24. 2013. Madrid)

Type: Conference paper


The different performance evolution betweenthe microprocessor and main memory is oneof the greatest challenges that current designers facein order to develop more powerful computer systems.In addition to this problem, called memory gap, thescalability of the Dynamic Random Access Memory(DRAM) technology is very limited nowadays, leadingto consider new memory technologies as possiblecandidates for the replacement of conventionalDRAM. Phase-Change Memory (PCM) is currentlypostulated as the best alternative.PCM exhibits significant advantages over DRAM,but also some drawbacks, like its low endurance –limited by the number of write cycles that can beperformed on each cell– that need to be mitigatedbefore it can be used as the main memory technologyfor the next computers generation. This workpresents a behavior analysis, in terms of number ofwrites to main memory, of some conventional cachereplacement policies. Besides, new last level cache(LLC) replacement algorithms are exposed, aimed atreducing the number of writes to PCM and hence increasingits lifetime, without significantly degradingthe system performance. In this paper we target embeddedprocessors with PCM main memory. Experimentalresults show that on average, compared to aconventional Least Recently Used (LRU) algorithm,our policies manage to reduce the amount of writesto main memory for MiBench and SPEC CPU2006suites by around 30% and 12% respectively, reducingsignificantly the energy consumption of the memorysystem and without degrading performance.