Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions

  1. Mallasen, David 2
  2. Murillo, Raul 1
  3. Del Barrio, Alberto A. 2
  4. Botella, Guillermo 3
  5. Pinuel, Luis 1
  6. Prieto-Matias, Manuel 3
  1. 1 Facultad de Ciencias Físicas Universidad Complutense de Madrid,Madrid,Spain,28040
  2. 2 Facultad de Informática Universidad Complutense de Madrid,Madrid,Spain,28040
  3. 3 Facultad de Informática Instituto de Tecnología del Conocimiento Universidad Complutense de Madrid,Madrid,Spain,28040
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Actas:
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

Editorial: IEEE

Año de publicación: 2022

Tipo: Aportación congreso

DOI: 10.1109/DCIS55711.2022.9970026 GOOGLE SCHOLAR lock_openAcceso abierto editor

Objetivos de desarrollo sostenible

Resumen

The posit representation for real numbers, aka Unum-v3, is an alternative to substitute the IEEE 754 standard and thus mitigate the inherent problems to the construction of floating-point numbers. Nonetheless, posits are not standard yet, and previously there was no approach, neither academically nor industrially, which implemented a fully compliant core for deploying this novel format. Recently, the open-source PERCIVAL posit RISC-V core was presented as the first work that fully integrates posit arithmetic and quire capabilities into hardware. In addition, Xposit, a RISC-V extension for posit operations allows for the compilation of C programs with inline assembly posit and quire instructions. As a study platform, PERCIVAL is based on the CVA6 core and has support for both posit and IEEE 754 formats, further permitting the comparison of these representations. This paper details the microarchitecture of the Posit Arithmetic Unit with quire added to this core. It also describes how to perform the necessary additions and modifications to the CVA6 core to add support for the Xposit RISC-V custom extension. Furthermore, FPGA synthesis results highlight the cost of including support for both posits with quire and IEEE 754 formats. This is done by breaking down the area resources needed for every arithmetic configuration.

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