A pseudo delay-insensitive timing model to synthesising low-power asynchronous circuits
- Garnica, O
- Lanchares, J
- Hermida, R
- Nebel, W (coord.)
- Jerraya, A (coord.)
ISBN: 0-7695-0994-0
Argitalpen urtea: 2001
Orrialdeak: 810-810
Biltzarra: Design, Automation and Test in Europe Conference and Exhibition (DATE 2001)
Mota: Biltzar ekarpena