Interconnection delay and clock cycle selection in high level synthesis

  1. Mecha, H
  2. Fernandez, M
Buch:
TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

ISBN: 0-8186-7755-4

Datum der Publikation: 1997

Seiten: 504-505

Kongress: 10th International Conference on VLSI Design

Art: Konferenz-Beitrag

DOI: 10.1109/ICVD.1997.568184 GOOGLE SCHOLAR
Fuente de los datos: WoS