Dieléctricos de alta permitividad para próximas generaciones de circuitos integrados/sHigh permitivity dielectrics for next generations of integrated circuit

  1. FEIJOO GUERRO, PEDRO CARLOS
Dirigée par:
  1. Enrique San Andres Serrano Directeur

Université de défendre: Universidad Complutense de Madrid

Fecha de defensa: 20 mars 2013

Jury:
  1. Germán González Díaz President
  2. Alvaro del Prado Millán Secrétaire
  3. Montserrat Nafria Maqueda Rapporteur
  4. Maria Toledano Luque Rapporteur
  5. Helena Castán Lanaspa Rapporteur

Type: Thèses

Résumé

This thesis studies two different approaches for further downscaling in the CMOS technology and the flash memory devices. In the first place, we study Gd2-xScxO3 deposited by high pressure sputtering as a candidate for the third generation of high k dielectrics. We studied the high k material/Si interface, and an optimization of the growing conditions of the binary components (Gd2O3 and Sc2O3). We assessed the influence of the metal gate on the properties of the binary oxides, comparing Al (reactive), Pt (noble metal) and Ti (oxygen scavenger). Then,we grew ~8 nm amorphous Gd-rich Gd2-xScxO3 films by alternating nano-laminates of Gd2O3 and Sc2O3. Pt gated metal-insulator-semiconductor devices show low density of interface defects, capacitance-voltage hysteresis and leakage current. Gd2-xScxO3 also presents better thermal stability than its binary components. An outstanding value of 25 was calculated for the relative effective permittivity, which makes Gd2-xScxO3 a promising choice for the third generation of high k dielectrics. On the other hand, we studied the reliability of ultra low equivalent oxide thickness triple gated MISFET devices. Three-dimensional transistor architectures are currently replacing traditional planar MISFETs, so the assessment of the reliability becomes vital. Time-dependent dielectric breakdown and positive bias temperature instabilities in FinFETs present no major differences with their planar counterparts.