Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

  1. Imana, J.L.
  2. Pinuel, L.
  3. Kuo, Y.
  4. Ruano, O.
  5. Garcia-Herrero, F.
IEEE Transactions on Circuits and Systems II: Express Briefs

ISSN: 1558-3791 1549-7747

Year of publication: 2024

Type: Article

DOI: 10.1109/TCSII.2024.3369103 GOOGLE SCHOLAR lock_openOpen access editor

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