Publicaciones en las que colabora con ROMÁN HERMIDA CORREA (81)

2014

  1. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power Optimization in Heterogenous Datapaths

    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)

  3. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE

2010

  1. Using Speculative Functional Units in High Level Synthesis

    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)

  2. Using speculative functional units in high level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2009

  1. A framework for low energy data management in reconfigurable multi-context architectures

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 127-139

  2. Frequent-pattern-guided multilevel decomposition of behavioral specifications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Núm. 1, pp. 60-73

2008

  1. A coarse-grain dynamically reconfigurable system and compilation framework

    Fine-and Coarse-Grain Reconfigurable Computing (Springer Netherlands), pp. 181-215

  2. Applying speculation techniques to implement functional units

    26th IEEE International Conference on Computer Design 2008, ICCD

  3. Exploiting bit-level design techniques in behavioural synthesis

    High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283

  4. Restricted chaining and fragmentation techniques in power aware high level synthesis

    Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

  5. Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures

    IET Computers and Digital Techniques, Vol. 2, Núm. 3, pp. 199-213

2007

  1. Area optimization of multi-cycle operators in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

  2. Area optimization of multi-cycle operators in high-level synthesis

    2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3

  3. HW-SW emulation framework for temperature-aware design in MPSoCs

    ACM Transactions on Design Automation of Electronic Systems

2006

  1. Bitwise scheduling to balance the computational cost of behavioral specifications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Núm. 1, pp. 31-46