JOSÉ FRANCISCO
TIRADO FERNÁNDEZ
Profesor emérito
KATZALIN
OLCOZ HERRERO
Profesora titular de universidad
Publikationen, an denen er mitarbeitet KATZALIN OLCOZ HERRERO (16)
2022
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Optimization of a line detection algorithm for autonomous vehicles on a RISC-V with accelerator
Journal of Computer Science and Technology, Vol. 22, Núm. 2
2020
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Leveraging knowledge-as-a-service (KaaS) for QoS-aware resource management in multi-user video transcoding
Journal of Supercomputing, Vol. 76, Núm. 12, pp. 9388-9403
2017
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Energy efficiency optimization of task-parallel codes on asymmetric architectures
Proceedings - 2017 International Conference on High Performance Computing and Simulation, HPCS 2017
2008
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Efficient object placement including node selection in a distributed virtual machine
Advances in Parallel Computing
2005
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Energy characterization of garbage collectors for dynamic applications on embedded systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2004
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Adaptive tuning of reserved space in an appel collector
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Adaptive tuning of reserved space in an appel collector
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3086, pp. 543-559
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Dynamic Optimization of Nursery Space Organization in Generational Collection
Computación de altas prestaciones: actas de las XV Jornadas de Paralelismo. Almería 15, 16 y 17 de septiembre de 2004
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Dynamic management of nursery space organization in generational collection
Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
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Garbage collector refinement for new dynamic multimedia applications on embedded systems
Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
1999
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Unified data path allocation and BIST intrusion
Integration, the VLSI Journal, Vol. 28, Núm. 1, pp. 55-99
1998
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Register allocation with simultaneous BIST intrusion
24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2
1996
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A method for area estimation of datapath in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 2, pp. 258265
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Method for area estimation of data-path in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 2, pp. 258-265
1994
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Integración del análisis y mejora de la testabilidad en una herramienta de SAN
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria
1993
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Data path structures and heuristics for testable allocation in high level synthesis
Microprocessing and Microprogramming, Vol. 39, Núm. 2-5, pp. 263-266