JUAN LANCHARES DÁVILA-rekin lankidetzan egindako argitalpenak (7)

2006

  1. A power-aware technique for functional units in high-performance processors

    Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

  2. A technique to reduce static and dynamic power of functional units in high-performance processors

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Comparing the performance of a 64-bit fully-asynchronous superscalar processor versus its synchronous counterpart

    Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

  4. Sim-async: An architectural simulator for asynchronous processor Modeling using distribution functions

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2005

  1. Adaptación de un simulador de potencia para unidades funcionales en procesadores de alto rendimiento

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  2. Métricas, metodologías y herramientas de simulación para evaluar mejoras en arquitecturas de bajo consumo

    Enlaces: revista del CES Felipe II, Núm. 3

  3. Power reduction of superscalar processor functional units by resizing adder-width

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)