Publicaciones en las que colabora con ROMÁN HERMIDA CORREA (36)

2014

  1. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power Optimization in Heterogenous Datapaths

    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)

  3. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE

2010

  1. Using Speculative Functional Units in High Level Synthesis

    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)

  2. Using speculative functional units in high level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2009

  1. Frequent-pattern-guided multilevel decomposition of behavioral specifications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Núm. 1, pp. 60-73

2008

  1. Applying speculation techniques to implement functional units

    26th IEEE International Conference on Computer Design 2008, ICCD

  2. Exploiting bit-level design techniques in behavioural synthesis

    High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283

  3. Restricted chaining and fragmentation techniques in power aware high level synthesis

    Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

2007

  1. Area optimization of multi-cycle operators in high-level synthesis

    2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3

  2. Area optimization of multi-cycle operators in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2006

  1. Bitwise scheduling to balance the computational cost of behavioral specifications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Núm. 1, pp. 31-46

  2. Pre-synthesis optimization of multiplications to improve circuit performance

    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS

  3. Pre-synthesis optimization of multiplications to improve circuit performance

    Proceedings -Design, Automation and Test in Europe, DATE

2005

  1. Arrival time aware scheduling to minimize clock cycle length

    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2

  2. Arrival time aware scheduling to minimize clock cycle length

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC