Publicaciones en las que colabora con JOSÉ MANUEL MENDÍAS CUADROS (32)

2014

  1. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE

2010

  1. Using speculative functional units in high level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2009

  1. Performance-driven scheduling of behavioural specifications

    Integration, the VLSI Journal, Vol. 42, Núm. 3, pp. 294-303

  2. Subword switching activity minimization to optimize dynamic power consumption

    IEEE Design and Test of Computers, Vol. 26, Núm. 4, pp. 68-77

2008

  1. Aerodynamics analysis acceleration through reconfigurable hardware

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. Applying speculation techniques to implement functional units

    26th IEEE International Conference on Computer Design 2008, ICCD

  3. Area optimization of combined integer and floating point circuits in high-level synthesis

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  4. Exploiting bit-level design techniques in behavioural synthesis

    High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283

  5. Restricted chaining and fragmentation techniques in power aware high level synthesis

    Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

2007

  1. Area optimization of multi-cycle operators in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

  2. Exploiting bit-level delay calculations to soften read-after-write dependences in behavioral synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Núm. 9, pp. 1589-1601

2006

  1. Bitwise scheduling to balance the computational cost of behavioral specifications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Núm. 1, pp. 31-46

  2. Pre-synthesis optimization of multiplications to improve circuit performance

    Proceedings -Design, Automation and Test in Europe, DATE

2005

  1. Arrival time aware scheduling to minimize clock cycle length

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

  2. Behavioural transformation to improve circuit performance in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE '05