MARÍA DEL CARMEN
MOLINA PREGO
Profesora titular de universidad
Publicaciones (46) Publicaciones de MARÍA DEL CARMEN MOLINA PREGO
2014
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Improving circuit performance with multispeculative additive trees in high-level synthesis
Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479
2013
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A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130
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Multispeculative additive trees in high-level synthesis
Proceedings -Design, Automation and Test in Europe, DATE
2012
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Multispeculative addition applied to datapath synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830
2011
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A distributed controller for managing speculative functional units in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363
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Power Optimization in Heterogenous Datapaths
2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)
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Power optimization in heterogenous datapaths
Proceedings -Design, Automation and Test in Europe, DATE
2010
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Robust bioinspired architecture for optical-flow computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, Núm. 4, pp. 616-629
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Using Speculative Functional Units in High Level Synthesis
2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
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Using speculative functional units in high level synthesis
Proceedings -Design, Automation and Test in Europe, DATE
2009
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Enhanced gradient-based motion vector coprocessor
FPL 09: 19th International Conference on Field Programmable Logic and Applications
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Frequent-pattern-guided multilevel decomposition of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Núm. 1, pp. 60-73
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Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal, Vol. 42, Núm. 3, pp. 294-303
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Subword switching activity minimization to optimize dynamic power consumption
IEEE Design and Test of Computers, Vol. 26, Núm. 4, pp. 68-77
2008
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Aerodynamics analysis acceleration through reconfigurable hardware
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL
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Applying speculation techniques to implement functional units
26th IEEE International Conference on Computer Design 2008, ICCD
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Area optimization of combined integer and floating point circuits in high-level synthesis
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL
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Exploiting bit-level design techniques in behavioural synthesis
High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283
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Exploiting internal operation patterns during the high-level synthesis of time-constrained circuits
Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
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FPGA based architecture for robust optical flow computation
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL