DANIEL ÁNGEL
CHAVER MARTÍNEZ
Profesor titular de universidad
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University of Rochester
Rochester, Estados UnidosPublications in collaboration with researchers from University of Rochester (9)
2009
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Replacing associative load queues: A timing-centric approach
IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511
2006
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DMDC: Delayed Memory Dependence Checking through age-based filtering
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
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LSQ: A power efficient and scalable implementation
IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398
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Substituting associative load queue with simple hash tables in out-of-order microprocessors
Proceedings of the International Symposium on Low Power Electronics and Design
2005
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A power-efficient and scalable load-store queue design
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Energy-aware fetch mechanism: Trace cache and BTB customization
Proceedings of the International Symposium on Low Power Electronics and Design
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Load-store queue management: An energy-efficient design based on a state-filtering mechanism
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
2003
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Branch Prediction On Demand: An Energy-Efficient Solution
Proceedings of the International Symposium on Low Power Electronics and Design
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Customizing the Branch Predictor to Reduce Complexity and Energy Consumption
IEEE Micro, Vol. 23, Núm. 5, pp. 12-25