Publications by the researcher in collaboration with ROMÁN HERMIDA CORREA (24)

2023

  1. HackRF + GNU Radio: A software-defined radio to teach communication theory

    International Journal of Electrical Engineering and Education, Vol. 60, Núm. 1, pp. 23-40

2019

  1. A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in datapaths

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Núm. 2, pp. 742-755

  2. Efficient mitchell's approximate log multipliers for convolutional neural networks

    IEEE Transactions on Computers, Vol. 68, Núm. 5, pp. 660-675

2018

  1. Complexity reduction in the HEVC/H265 standard based on smooth region classification

    Digital Signal Processing: A Review Journal, Vol. 73, pp. 24-39

  2. Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks

    2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)

  3. Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

2017

  1. A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers

    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

  2. A slack-based approach to efficiently deploy radix 8 booth multipliers

    Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

2016

  1. A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, Núm. 3, pp. 419-432

  2. A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

    IEEE Transactions on Computers, Vol. 65, Núm. 11, pp. 3251-3264

2014

  1. Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer

    Digital Signal Processing: A Review Journal, Vol. 33, pp. 191-205

  2. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

  3. Ultra-low-power adder stage design for exascale floating point units

    ACM Transactions on Embedded Computing Systems

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Exploring the energy efficiency of multispeculative adders

    2013 IEEE 31st International Conference on Computer Design, ICCD 2013

  3. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power Optimization in Heterogenous Datapaths

    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)

  3. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE