Publications by the researcher in collaboration with MARÍA DEL CARMEN MOLINA PREGO (14)

2014

  1. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power Optimization in Heterogenous Datapaths

    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)

  3. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE

2010

  1. Using Speculative Functional Units in High Level Synthesis

    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)

  2. Using speculative functional units in high level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2009

  1. Subword switching activity minimization to optimize dynamic power consumption

    IEEE Design and Test of Computers, Vol. 26, Núm. 4, pp. 68-77

2008

  1. Aerodynamics analysis acceleration through reconfigurable hardware

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. Applying speculation techniques to implement functional units

    26th IEEE International Conference on Computer Design 2008, ICCD

  3. Area optimization of combined integer and floating point circuits in high-level synthesis

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  4. Restricted chaining and fragmentation techniques in power aware high level synthesis

    Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008