JOSÉ MANUEL
MENDÍAS CUADROS
Catedrático de universidad
MARÍA DEL CARMEN
MOLINA PREGO
Profesora titular de universidad
MARÍA DEL CARMEN MOLINA PREGO-rekin lankidetzan egindako argitalpenak (32)
2014
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Improving circuit performance with multispeculative additive trees in high-level synthesis
Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479
2013
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A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130
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Multispeculative additive trees in high-level synthesis
Proceedings -Design, Automation and Test in Europe, DATE
2012
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Multispeculative addition applied to datapath synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830
2011
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A distributed controller for managing speculative functional units in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363
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Power optimization in heterogenous datapaths
Proceedings -Design, Automation and Test in Europe, DATE
2010
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Using speculative functional units in high level synthesis
Proceedings -Design, Automation and Test in Europe, DATE
2009
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Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal, Vol. 42, Núm. 3, pp. 294-303
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Subword switching activity minimization to optimize dynamic power consumption
IEEE Design and Test of Computers, Vol. 26, Núm. 4, pp. 68-77
2008
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Aerodynamics analysis acceleration through reconfigurable hardware
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL
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Applying speculation techniques to implement functional units
26th IEEE International Conference on Computer Design 2008, ICCD
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Area optimization of combined integer and floating point circuits in high-level synthesis
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL
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Exploiting bit-level design techniques in behavioural synthesis
High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283
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Restricted chaining and fragmentation techniques in power aware high level synthesis
Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
2007
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Area optimization of multi-cycle operators in high-level synthesis
Proceedings -Design, Automation and Test in Europe, DATE
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Exploiting bit-level delay calculations to soften read-after-write dependences in behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Núm. 9, pp. 1589-1601
2006
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Bitwise scheduling to balance the computational cost of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Núm. 1, pp. 31-46
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Pre-synthesis optimization of multiplications to improve circuit performance
Proceedings -Design, Automation and Test in Europe, DATE
2005
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Arrival time aware scheduling to minimize clock cycle length
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
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Behavioural transformation to improve circuit performance in high-level synthesis
Proceedings -Design, Automation and Test in Europe, DATE '05