University of California, Irvine-ko ikertzaileekin lankidetzan egindako argitalpenak (41)

2022

  1. PLAM: A Posit Logarithm-Approximate Multiplier

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 4, pp. 2079-2085

  2. The Effects of Approximate Multiplication on Convolutional Neural Networks

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 904-916

2019

  1. A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks

    Proceedings - Symposium on Computer Arithmetic

  2. Design of power-efficient FPGA convolutional cores with approximate log multiplier

    ESANN 2019 - Proceedings, 27th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

  3. Efficient mitchell's approximate log multipliers for convolutional neural networks

    IEEE Transactions on Computers, Vol. 68, Núm. 5, pp. 660-675

2018

  1. Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks

    2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)

  2. Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

2017

  1. Special issue on energy efficient multi-core and many-core systems, Part II

    Journal of Parallel and Distributed Computing

2016

  1. Special issue on energy efficient multi-core and many-core systems, Part I

    Journal of Parallel and Distributed Computing

2014

  1. Ultra-low-power adder stage design for exascale floating point units

    ACM Transactions on Embedded Computing Systems

2009

  1. A framework for low energy data management in reconfigurable multi-context architectures

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 127-139

2008

  1. A coarse-grain dynamically reconfigurable system and compilation framework

    Fine-and Coarse-Grain Reconfigurable Computing (Springer Netherlands), pp. 181-215

  2. A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

    International Journal of Embedded Systems, Vol. 3, Núm. 4, pp. 285-293

  3. Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures

    IET Computers and Digital Techniques, Vol. 2, Núm. 3, pp. 199-213

2006

  1. Configuration scheduling for conditional branch execution onto multi-context reconfigurable architectures

    Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

  2. Configuration scheduling for conditional branch execution onto multi-context reconfigurable architectures

    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS

  3. Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)

    Proceedings -Design, Automation and Test in Europe, DATE

  4. Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)

    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS

2005

  1. A low energy data management for multi-context reconfigurable architectures

    New Algorithms, Architectures and Applications for Reconfigurable Computing (Springer US), pp. 145-155

  2. An approach to execute conditional branches onto SIMD multi-context reconfigurable architectures

    Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools