Publicaciones en las que colabora con Luis Parrilla Roure (7)

2017

  1. A new area-efficient BCD-digit multiplier

    Digital Signal Processing: A Review Journal, Vol. 62, pp. 1-10

2015

  1. Improvements for the applicability of power-watermarking to embedded IP cores protection: E-coreIPP

    Digital Signal Processing: A Review Journal, Vol. 44, Núm. 1, pp. 110-122

2013

  1. Efficient wavelet-based ECG processing for single-lead FHR extraction

    Digital Signal Processing: A Review Journal, Vol. 23, Núm. 6, pp. 1897-1909

2011

  1. Intellectual Property Protection (IPP) using obfuscation in C, VHDL, and Verilog coding

    Proceedings of SPIE - The International Society for Optical Engineering

2009

  1. Enhanced gradient-based motion vector coprocessor

    FPL 09: 19th International Conference on Field Programmable Logic and Applications

2008

  1. Automated signature insertion in combinational logic patterns for HDL IP core protection

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. FPGA based architecture for robust optical flow computation

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL