Publicaciones en las que colabora con JULIO SEPTIEN DEL CASTILLO (31)

2009

  1. 3D FPGA resource management and fragmentation metric for hardware multitasking

    IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

2008

  1. Allocation heuristics and defragmentation measures for reconfigurable systems management

    Integration, the VLSI Journal, Vol. 41, Núm. 2, pp. 281-296

  2. Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays

    IET Computers and Digital Techniques, Vol. 2, Núm. 6, pp. 401-412

  3. FPGA resource management using internal RAM as data cache

    Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

  4. Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking

    IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

  5. Resource management for HW multitasking in three dimensional FPGAs

    Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

  6. Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system

    Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

2006

  1. 2D defragmentation heuristics for hardware multitasking on reconfigurable devices

    20th International Parallel and Distributed Processing Symposium, IPDPS 2006

  2. Constant complexity management of 2D HW multitasking in run-time reconfigurable FPGAs

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Partition based dynamic 2D HW multitasking management

    Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

  4. Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

2004

  1. A low fragmentation heuristic for task placement in 2D RTR HW management

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, pp. 241-250

2003

  1. A hardware/software partitioning and scheduling approach for embedded systems with low-power and high performance requirements

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2799, pp. 580-589

  2. Analyzing communication overheads during hardware/software partitioning

    Microelectronics Journal, Vol. 34, Núm. 11, pp. 1001-1007

2002

  1. Planificación de las comunicaciones en un entorno de codiseño hardware/software

    SAAEI'02: IX Seminario Anual de Automática, Electrónica Industrial e Instrumentación, Universidad de Alcalá, Alcalá de Henares, 18, 19 y 20 de septiembre de 2002

1998

  1. A grouping partitioning technique with automatic criterion selection for the codesign process

    Proceedings - 24th EUROMICRO Conference, EURMIC 1998

1996

  1. A method for area estimation of datapath in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 2, pp. 258265

  2. Method for area estimation of data-path in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 2, pp. 258-265

1995

  1. FIDIAS: an integral approach to high-level synthesis

    IEE Proceedings: Circuits, Devices and Systems, Vol. 142, Núm. 4, pp. 227-235

1994

  1. Un método de estimación de área en síntesis de alto nivel

    Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria