Antonio García Ríos-rekin lankidetzan egindako argitalpenak (19)

2017

  1. A new area-efficient BCD-digit multiplier

    Digital Signal Processing: A Review Journal, Vol. 62, pp. 1-10

  2. Dynamical graph theory networks techniques for the analysis of sparse connectivity networks in dementia

    Proceedings of SPIE - The International Society for Optical Engineering

  3. The driving regulators of the connectivity protein network of brain malignancies

    Proceedings of SPIE - The International Society for Optical Engineering

2015

  1. Improvements for the applicability of power-watermarking to embedded IP cores protection: E-coreIPP

    Digital Signal Processing: A Review Journal, Vol. 44, Núm. 1, pp. 110-122

2013

  1. Efficient wavelet-based ECG processing for single-lead FHR extraction

    Digital Signal Processing: A Review Journal, Vol. 23, Núm. 6, pp. 1897-1909

2012

  1. A reconstruction method for electrical capacitance tomography based on image fusion techniques

    Digital Signal Processing: A Review Journal, Vol. 22, Núm. 6, pp. 885-893

  2. Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology

    Microprocessors and Microsystems

  3. Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture

    Digital Signal Processing: A Review Journal, Vol. 22, Núm. 6, pp. 1174-1187

2011

  1. Intellectual Property Protection (IPP) using obfuscation in C, VHDL, and Verilog coding

    Proceedings of SPIE - The International Society for Optical Engineering

2010

  1. A balanced HW/SW teaching approach for embedded microprocessors

    International Journal of Engineering Education, Vol. 26, Núm. 3, pp. 584-592

  2. Nios II hardware acceleration of the epsilon quadratic sieve algorithm

    Proceedings of SPIE - The International Society for Optical Engineering

  3. Robust bioinspired architecture for optical-flow computation

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, Núm. 4, pp. 616-629

2009

  1. Bio-inspired robust optical flow processor system for VLSI implementation

    Electronics Letters, Vol. 45, Núm. 25, pp. 1304-1305

  2. DSP structure to motion computation on reconfigurable hardware

    Proceedings of SPIE - The International Society for Optical Engineering

  3. Enhanced gradient-based motion vector coprocessor

    FPL 09: 19th International Conference on Field Programmable Logic and Applications

2008

  1. Automated signature insertion in combinational logic patterns for HDL IP core protection

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. FPGA based architecture for robust optical flow computation

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

2006

  1. Pre-processor for bioinspired optical flow models: A customizable hardware implementation

    Proceedings of the Mediterranean Electrotechnical Conference - MELECON

  2. Pre-processor for bioinspired optical flow models: A customizable hardware implementation.

    CIRCUITS AND SYSTEMS FOR SIGNAL PROCESSING , INFORMATION AND COMMUNICATION TECHNOLOGIES, AND POWER SOURCES AND SYSTEMS, VOL 1 AND 2, PROCEEDINGS