Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

  1. Artes, A.
  2. Ayala, J.L.
  3. Sathanur, A.V.
  4. Huisken, J.
  5. Catthoor, F.
Actes de conférence:
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

ISBN: 9781457701719

Année de publication: 2011

Pages: 136-141

Type: Communication dans un congrès

DOI: 10.1109/VLSISOC.2011.6081635 GOOGLE SCHOLAR