Design of a pipelined hardware architecture for real-time neural network computations

  1. Ayala, J.L.
  2. Lomeña, A.G.
  3. López-Vallejo, M.
  4. Fernández, A.
Aldizkaria:
Midwest Symposium on Circuits and Systems

Argitalpen urtea: 2002

Alea: 1

Orrialdeak: I419-I422

Mota: Artikulua

DOI: 10.1109/MWSCAS.2002.1187247 GOOGLE SCHOLAR
Datuen iturria: Scopus