Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 fieldprogrammable gate array

  1. Olivito, J.
  2. Serrano, F.
  3. Clemente, J.A.
  4. Mecha, H.
  5. Resano, J.
IET Computers and Digital Techniques

ISSN: 1751-8601

Year of publication: 2018

Volume: 12

Issue: 4

Pages: 150-157

Type: Article

DOI: 10.1049/IET-CDT.2016.0095 GOOGLE SCHOLAR