A pseudo delay-insensitive timing model to synthesising low-power asynchronous circuits

  1. Garnica, O
  2. Lanchares, J
  3. Hermida, R
Libro:
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS
  1. Nebel, W (coord.)
  2. Jerraya, A (coord.)

ISBN: 0-7695-0994-0

Año de publicación: 2001

Páginas: 810-810

Congreso: Design, Automation and Test in Europe Conference and Exhibition (DATE 2001)

Tipo: Aportación congreso

GOOGLE SCHOLAR
Fuente de los datos: WoS