F.
Catthoor
Publicaciones en las que colabora con F. Catthoor (33)
2015
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Placement of linked dynamic data structures over heterogeneous memories in embedded systems
ACM Transactions on Embedded Computing Systems, Vol. 14, Núm. 2, pp. 37
2014
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Configuration mapping algorithms to reduce energy and time reconfiguration overheads in reconfigurable systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1248-1261
2010
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Software metadata: Systematic characterization of the memory behaviour of dynamic applications
Journal of Systems and Software, Vol. 83, Núm. 6, pp. 1051-1075
2008
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Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 4
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Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded Software Metadata Information
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2007
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Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Memory hierarchy for high-performance and energy-aware reconfigurable systems
IET Computers and Digital Techniques, Vol. 1, Núm. 5, pp. 565-571
2006
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A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
20th International Parallel and Distributed Processing Symposium, IPDPS 2006
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Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems
Proceedings -Design, Automation and Test in Europe, DATE
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Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
Integration, the VLSI Journal, Vol. 39, Núm. 2, pp. 113-130
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Systematic dynamic memory management design methodology for reduced memory footprint
ACM Transactions on Design Automation of Electronic Systems, Vol. 11, Núm. 2, pp. 465-489
2005
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A complete network-on-chip emulation framework
Proceedings -Design, Automation and Test in Europe, DATE '05
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A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware
Proceedings -Design, Automation and Test in Europe, DATE '05
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A novel approach for network on chip emulation
Proceedings - IEEE International Symposium on Circuits and Systems
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A reconfiguration manager for dynamically reconfigurable hardware
IEEE Design and Test of Computers, Vol. 22, Núm. 5, pp. 452-460
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Energy characterization of garbage collectors for dynamic applications on embedded systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Methodology for refinement and optimisation of dynamic memory management for embedded systems in multimedia applications
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
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Reducing memory fragmentation with performance-optimized dynamic memory allocators in network applications
Lecture Notes in Computer Science
2004
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A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
Microprocessors and Microsystems, Vol. 28, Núm. 5-6 SPEC. ISS., pp. 291-301
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An integrated hardware/software approach for run-time scratchpad management
Proceedings - Design Automation Conference