Grupo de gestión de hardware reconfigurable
Universidad Francisco de Vitoria
Pozuelo de Alarcón, EspañaPublicaciones en colaboración con investigadores/as de Universidad Francisco de Vitoria (4)
2024
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Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital
Microprocessors and Microsystems, Vol. 105
2022
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Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories
IEEE Access, Vol. 10, pp. 114566-114585
2016
2013
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An efficient technique to protect serial shift registers against soft errors
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, Núm. 8, pp. 512-516