Publicaciones en colaboración con investigadores/as de KU Leuven (22)

2014

  1. Configuration mapping algorithms to reduce energy and time reconfiguration overheads in reconfigurable systems

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1248-1261

2010

  1. Software metadata: Systematic characterization of the memory behaviour of dynamic applications

    Journal of Systems and Software, Vol. 83, Núm. 6, pp. 1051-1075

2008

  1. Efficiently scheduling runtime reconfigurations

    ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 4

  2. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded Software Metadata Information

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

2007

  1. Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Memory hierarchy for high-performance and energy-aware reconfigurable systems

    IET Computers and Digital Techniques, Vol. 1, Núm. 5, pp. 565-571

2006

  1. A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead

    20th International Parallel and Distributed Processing Symposium, IPDPS 2006

  2. Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems

    Proceedings -Design, Automation and Test in Europe, DATE

  3. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems

    Integration, the VLSI Journal, Vol. 39, Núm. 2, pp. 113-130

2005

  1. A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware

    Proceedings -Design, Automation and Test in Europe, DATE '05

  2. A reconfiguration manager for dynamically reconfigurable hardware

    IEEE Design and Test of Computers, Vol. 22, Núm. 5, pp. 452-460

  3. Methodology for refinement and optimisation of dynamic memory management for embedded systems in multimedia applications

    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

  4. Reducing memory fragmentation with performance-optimized dynamic memory allocators in network applications

    Lecture Notes in Computer Science

2004

  1. A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

    Microprocessors and Microsystems, Vol. 28, Núm. 5-6 SPEC. ISS., pp. 291-301

  2. Design of energy efficient wireless networks using dynamic data type refinement methodology

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2957, pp. 26-37

  3. Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices

    2004 IEEE International Conference on Multimedia and Expo (ICME)

  4. Memory-Access-Aware Data Structure Transformations for Embedded Software With Dynamic Data Accesses

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

  5. Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware

    Proceedings - Design Automation Conference

2003

  1. Application of task concurrency management on dynamically reconfigurable hardware platforms

    IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

  2. Methodology for refinement and optimization of dynamic memory management for embedded systems in multimedia applications

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation