Publicaciones en las que colabora con MANUEL PRIETO MATÍAS (22)

2022

  1. LFOC+: A Fair OS-Level Cache-Clustering Policy for Commodity Multicore Systems

    IEEE Transactions on Computers, Vol. 71, Núm. 8, pp. 1952-1967

2020

  1. Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors

    ACM International Conference Proceeding Series

2019

  1. LFOC: A lightweight fairness-oriented cache clustering policy for commodity multicores

    ACM International Conference Proceeding Series

  2. Particionado eficiente de cache en cluster para mejorar la justicia en procesadores multicore comerciales

    Avances en Arquitectura y Tecnología de Computadores: Actas de Jornadas SARTECO, Cáceres, 18 a 20 de septiembre de 2019| (Servicio de Publicaciones), pp. 162-171

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2017

  1. PMCTrack: Delivering performance monitoring counter support to the OS scheduler

    Computer Journal, Vol. 60, Núm. 1, pp. 60-85

  2. Towards completely fair scheduling on asymmetric single-ISA multicore processors

    Journal of Parallel and Distributed Computing, Vol. 102, pp. 115-131

2015

  1. ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems

    Proceedings of the ACM Symposium on Applied Computing

  2. An OS-Oriented performance monitoring tool for multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2014

  1. Exploring the throughput-fairness trade-off on asymmetric multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2013

  1. Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling

    Performance Evaluation Review

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. DMDC: Delayed Memory Dependence Checking through age-based filtering

    MICRO-39: PROCEEDINGS OF THE 39TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE

  3. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398

  4. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    Proceedings of the International Symposium on Low Power Electronics and Design

  5. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    ISLPED '06: PROCEEDINGS OF THE 2006 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN

2005

  1. A power-efficient and scalable load-store queue design

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)