Publicacions en què col·labora amb María del Pilar Parra Fernández (7)

2007

  1. A methodology for switching noise estimation at gate level

    Proceedings of SPIE - The International Society for Optical Engineering

  2. A switching noise vision of the optimization techniques for low-power synthesis

    European Conference on Circuit Theory and Design 2007, ECCTD 2007

  3. Asymmetric clock driver for improved power and noise performances

    Proceedings - IEEE International Symposium on Circuits and Systems

  4. Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

    Proceedings of SPIE - The International Society for Optical Engineering

2006

  1. Optimization of master-slave flip-flops for high-performance applications

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2005

  1. Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits

    Proceedings of SPIE - The International Society for Optical Engineering

  2. Performance analysis of full adders in CMOS technologies

    Proceedings of SPIE - The International Society for Optical Engineering