Publicaciones en colaboración con investigadores/as de Interuniversity Microelectronics Centre (12)

2023

  1. COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

    Journal of Systems Architecture, Vol. 145

2022

  1. Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

    ACM Transactions on Embedded Computing Systems, Vol. 21, Núm. 1

2019

  1. A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs

    Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

2018

  1. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

2017

  1. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    Proceedings - IEEE International Symposium on Circuits and Systems

2015

  1. System level exploration of a STT-MRAM based level 1 data-cache

    Proceedings -Design, Automation and Test in Europe, DATE

2014

  1. Feasibility exploration of NVM based I-cache through MSHR enhancements

    Proceedings -Design, Automation and Test in Europe, DATE

2013

  1. Design exploration of a NVM based hybrid instruction memory organization for embedded platforms

    Design Automation for Embedded Systems, Vol. 7, Núm. 5, pp. 459-483

  2. Polyhedral parallel code generation for CUDA

    Transactions on Architecture and Code Optimization, Vol. 9, Núm. 4

  3. System-level memory management based on statistical variability compensation for frame-based applications

    Transactions on Embedded Computing Systems

2010

  1. Statistical approach in a system level methodology to deal with process variation

    Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

2005

  1. Improving superword level parallelism support in modern compilers

    CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis