Publicaciones en colaboración con investigadores/as de Universidad de Zaragoza (7)

2018

  1. Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 fieldprogrammable gate array

    IET Computers and Digital Techniques, Vol. 12, Núm. 4, pp. 150-157

2016

  1. Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 2, pp. 530-543

2014

  1. An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems

    ACM Transactions on Embedded Computing Systems, Vol. 13, Núm. 4

  2. Configuration mapping algorithms to reduce energy and time reconfiguration overheads in reconfigurable systems

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1248-1261

2011

  1. A Hardware implementation of a run-time scheduler for reconfigurable systems

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, Núm. 7, pp. 1263-1276

  2. A replacement technique to maximize task reuse in reconfigurable systems

    IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum

2010

  1. A task graph execution manager for reconfigurable multi-tasking systems

    Microprocessors and Microsystems, Vol. 34, Núm. 2-4, pp. 73-83