Publicaciones en colaboración con investigadores/as de University of Bologna (20)

2020

  1. Impact of memory voltage scaling on accuracy and resilience of deep learning based edge devices

    IEEE Design and Test, Vol. 37, Núm. 2, pp. 84-92

2018

  1. Energy Proportionality in Near-Threshold Computing Servers and Cloud Data Centers: Consolidating or Not?

    PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

2016

  1. Towards Near-Threshold Server Processors

    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

2014

  1. Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

    PROCEEDINGS OF THE 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED)

2012

  1. Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

    DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)

2011

  1. Thermal-Aware System-Level Modeling and Management for Multi-Processor Systems-on-Chip

    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

2009

  1. Multicore Thermal Management with Model Predictive Control

    2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2

  2. Prediction and Management in Energy Harvested Wireless Sensor Nodes

    2009 1ST INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATION, VEHICULAR TECHNOLOGY, INFORMATION THEORY AND AEROSPACE & ELECTRONIC SYSTEMS TECHNOLOGY, VOLS 1 AND 2

2008

  1. Designing routing and message-dependent deadlock free Networks on Chips

    VLSI-SOC: RESEARCH TRENDS IN VLSI AND SYSTEMS ON CHIP

  2. Thermal balancing policy for streaming computing on multiprocessor architectures

    2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3

2007

  1. Improving the fault tolerance of nanometric PLA designs

    2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3

  2. NoC design and implementation in 65nm technology

    NOCS 2007: FIRST INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS

  3. Reliability support for on-chip memories using Networks-on-Chip

    PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN

  4. System-level design for nano-electronics

    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4

2006

  1. A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip

    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006

  2. A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006

  3. Comparison of a timing-error tolerant scheme with a traditional re-transmission mechanism for networks on chips

    2006 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP PROCEEDINGS

  4. Designing application-specific networks on chips with floorplan information

    IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD

  5. Designing message-dependent deadlock free networks on chips for application-specific systems on chips

    IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP

2004

  1. An integrated hardware/software approach for run-time scratchpad management

    41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004