Publicaciones en las que colabora con RAÚL MURILLO MONTERO (14)

2024

  1. HUB Meets Posit: Arithmetic Units Implementation

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 71, Núm. 1, pp. 440-444

2023

  1. A Suite of Division Algorithms for Posit Arithmetic

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

  2. Generating Posit-Based Accelerators with High-Level Synthesis

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 70, Núm. 10, pp. 4040-4052

  3. PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core

    Proceedings of the 20th ACM International Conference on Computing Frontiers 2023, CF 2023

  4. PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2022

  1. Comparing Different Decodings for Posit Arithmetic

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions

    2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

  3. PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 3, pp. 1241-1252

  4. PLAM: A Posit Logarithm-Approximate Multiplier

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 4, pp. 2079-2085

  5. THE EFFECTS OF NUMERICAL PRECISION IN SCIENTIFIC APPLICATIONS

    Simulation Series

  6. The Effects of Numerical Precision In Scientific Applications

    Proceedings of the 2022 Annual Modeling and Simulation Conference, ANNSIM 2022

2021

  1. Energy-Efficient MAC Units for Fused Posit Arithmetic

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

2020

  1. Customized posit adders and multipliers using the FloPoCo core generator

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. Deep PeNSieve: A deep learning framework based on the posit number system

    Digital Signal Processing: A Review Journal, Vol. 102