Publicaciones en las que colabora con ANTONIO ÓSCAR GARNICA ALCÁZAR (12)

2004

  1. Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays

    12TH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, PROCEEDINGS

  2. Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays

    Proceedings - Euromicro Conference on Parellel, Distribeted and Network-based Proceeding

2003

  1. Multi-FPGA systems synthesis by means of evolutionary computation

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2724, pp. 2109-2120

  2. Power-consumption reduction in asynchronous circuits using delay path unequalization

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2799, pp. 151-160

2002

  1. A new methodology to design low-power asynchronous circuits

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Optimization of asynchronous delay-insensitive pipeline latency using stage reorganization and optimal stage parameter estimation

    Fundamenta Informaticae, Vol. 50, Núm. 2, pp. 155-174

2001

  1. A pseudo delay-insensitive timing model to synthesising low-power asynchronous circuits

    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS

  2. A pseudo relay-insensitive timing model to synthesising low-power asynchronous circuits

    Proceedings -Design, Automation and Test in Europe, DATE

  3. Optimization of asynchronous delay-insensitive pipeline latency using stage reorganization and optimal stage parameter estimation

    SECOND INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEMS DESIGN, PROCEEDINGS

  4. Optimization of asynchronous delay-insensitive pipeline latency using stage reorganization and optimal stage parameter estimation

    Proceedings - International Conference on Application of Concurrency to System Design, ACSD

2000

  1. Fine-grain asynchronous circuits for low-power high performance DSP implementations

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

  2. Fine-grain asynchronous circuits for low-power high performance dsp implementations

    2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION