DANIEL ÁNGEL
CHAVER MARTÍNEZ
Profesor titular de universidad
MANUEL
PRIETO MATÍAS
Catedrático de universidad
Publicaciones en las que colabora con MANUEL PRIETO MATÍAS (26)
2018
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Reuse Detector: Improving the Management of STT-RAM SLLCs
Computer Journal, Vol. 61, Núm. 6, pp. 856-880
2017
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Towards completely fair scheduling on asymmetric single-ISA multicore processors
Journal of Parallel and Distributed Computing, Vol. 102, pp. 115-131
2015
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ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems
Proceedings of the ACM Symposium on Applied Computing
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An OS-Oriented performance monitoring tool for multicore systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2014
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Exploring the throughput-fairness trade-off on asymmetric multicore systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2013
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Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling
Performance Evaluation Review
2011
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Hybrid timing-address oriented load-store queue filtering for an x86 architecture
IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157
2009
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Replacing associative load queues: A timing-centric approach
IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511
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Using age registers for a simple load-store queue filtering
Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89
2008
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Energy reduction of the fetch mechanism through dynamic adaptation
IET Computers and Digital Techniques, Vol. 2, Núm. 2, pp. 94-107
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Memory disambiguation hardware: a Review
Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138
2006
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DMDC: Delayed Memory Dependence Checking through age-based filtering
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
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LSQ: A power efficient and scalable implementation
IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398
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Substituting associative load queue with simple hash tables in out-of-order microprocessors
Proceedings of the International Symposium on Low Power Electronics and Design
2005
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A Per-Module adaptive fetch mechanism
Actas de las XVI Jornadas de Paralelismo. [JP'2005]
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A power-efficient and scalable load-store queue design
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Energy-aware fetch mechanism: Trace cache and BTB customization
Proceedings of the International Symposium on Low Power Electronics and Design
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Gestión eficiente de la LSQ basada en mecanismos de filtrado
Actas de las XVI Jornadas de Paralelismo. [JP'2005]
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Load-store queue management: An energy-efficient design based on a state-filtering mechanism
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
2003
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Branch Prediction On Demand: An Energy-Efficient Solution
Proceedings of the International Symposium on Low Power Electronics and Design