Publicacións (43) Publicacións de DANIEL ÁNGEL CHAVER MARTÍNEZ

2023

  1. RVfpga: Computer Architecture Course and MOOC Using a RISC-V SoC Targeted to an FPGA and Simulation

    ASEE Annual Conference and Exposition, Conference Proceedings

2021

  1. RVFPGA: Using a RISC-V core targeted to an FPGA in computer architecture education

    Proceedings - 2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2017

  1. MIPSfpga: Using a commercial MIPS soft-core in computer architecture education

    IET Circuits, Devices and Systems, Vol. 11, Núm. 4, pp. 283-291

  2. Practical experiences based on MIPSfpga

    Proceedings of the 19th Workshop on Computer Architecture Education, WCAE 2017

  3. Towards completely fair scheduling on asymmetric single-ISA multicore processors

    Journal of Parallel and Distributed Computing, Vol. 102, pp. 115-131

  4. Uso de la infraestructura docente MIPSfpga v2.0 en la asignatura Arquitectura de Sistemas Integrados

    Enseñanza y aprendizaje de ingeniería de computadores: Revista de Experiencias Docentes en Ingeniería de Computadores, Núm. 7, pp. 21-36

2016

  1. MIPSfpga: Hands-on learning on a commercial soft-core

    2016 11th European Workshop on Microelectronics Education, EWME 2016

  2. OpenIRS-UCM: An Integral Solution for Interactive Response Systems

    International Journal of Engineering Education, Vol. 32, Núm. 2, pp. 873-885

2015

  1. ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems

    Proceedings of the ACM Symposium on Applied Computing

  2. An OS-Oriented performance monitoring tool for multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2014

  1. Exploring the throughput-fairness trade-off on asymmetric multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Improving peLIFO cache replacement policy: Hardware reduction and thread-aware extension

    Journal of Circuits, Systems and Computers, Vol. 23, Núm. 4

  3. Write-aware replacement policies for PCM-based systems

    Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025

2013

  1. Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling

    Performance Evaluation Review

  2. Explotando el Compromiso Rendimiento-Justicia en Procesadores Multicore Asimétricos mediante Planificación

    Actas de las XXIV Jornadas de Paralelismo

  3. Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

    Actas de las XXIV Jornadas de Paralelismo

  4. Reducing writes in phase-change memory environments by using efficient cache replacement policies

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. OpenIRS-UCM: An open-source multi-platform for interactive response systems

    Annual Conference on Innovation and Technology in Computer Science Education, ITiCSE

  2. Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

    Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7