Publicaciones (74) Publicaciones de JOSÉ MANUEL MENDÍAS CUADROS

2015

  1. Placement of linked dynamic data structures over heterogeneous memories in embedded systems

    ACM Transactions on Embedded Computing Systems, Vol. 14, Núm. 2, pp. 37

2014

  1. Improving circuit performance with multispeculative additive trees in high-level synthesis

    Microelectronics Journal, Vol. 45, Núm. 11, pp. 1470-1479

2013

  1. A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

    Integration, the VLSI Journal, Vol. 46, Núm. 2, pp. 119-130

  2. Multispeculative additive trees in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Multispeculative addition applied to datapath synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Núm. 12, pp. 1817-1830

2011

  1. A distributed controller for managing speculative functional units in high level synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Núm. 3, pp. 350-363

  2. Power optimization in heterogenous datapaths

    Proceedings -Design, Automation and Test in Europe, DATE

2010

  1. Software metadata: Systematic characterization of the memory behaviour of dynamic applications

    Journal of Systems and Software, Vol. 83, Núm. 6, pp. 1051-1075

  2. Using speculative functional units in high level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

2009

  1. Performance-driven scheduling of behavioural specifications

    Integration, the VLSI Journal, Vol. 42, Núm. 3, pp. 294-303

  2. Subword switching activity minimization to optimize dynamic power consumption

    IEEE Design and Test of Computers, Vol. 26, Núm. 4, pp. 68-77

2008

  1. Aerodynamics analysis acceleration through reconfigurable hardware

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. Applying speculation techniques to implement functional units

    26th IEEE International Conference on Computer Design 2008, ICCD

  3. Area optimization of combined integer and floating point circuits in high-level synthesis

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  4. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded Software Metadata Information

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

  5. Exploiting bit-level design techniques in behavioural synthesis

    High-Level Synthesis: From Algorithm to Digital Circuit (Springer Netherlands), pp. 257-283

  6. Restricted chaining and fragmentation techniques in power aware high level synthesis

    Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

2007

  1. Area optimization of multi-cycle operators in high-level synthesis

    Proceedings -Design, Automation and Test in Europe, DATE

  2. Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Exploiting bit-level delay calculations to soften read-after-write dependences in behavioral synthesis

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Núm. 9, pp. 1589-1601