FRANCISCO MIGUEL
GARCÍA HERRERO
Profesor titular de universidad
Universidad Politécnica de Valencia
Valencia, EspañaPublications en collaboration avec des chercheurs de Universidad Politécnica de Valencia (30)
2024
2023
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Layered Decoding of Quantum LDPC Codes
2023 12th International Symposium on Topics in Coding, ISTC 2023
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Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures
EPJ Quantum Technology, Vol. 10, Núm. 1
2021
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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes
IEEE Access, Vol. 9, pp. 138734-138743
2019
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A test vector generation method based on symbol error probabilities for low-complexity chase soft-decision reed-solomon decoding
IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Núm. 6, pp. 2198-2207
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Reed–Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems
Circuits, Systems, and Signal Processing, Vol. 38, Núm. 4, pp. 1793-1810
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Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes
Circuits, Systems, and Signal Processing, Vol. 38, Núm. 11, pp. 5068-5080
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Soft-decision low-complexity chase decoders for the RS(255,239) code
Electronics (Switzerland), Vol. 8, Núm. 1
2018
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High-throughput one-channel RS(255,239) Decoder
Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
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Soft-decision LCC Decoder Architecture with η=4 for RS(255,239)
2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018
2017
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Algorithms and VLSI architectures for low-density parity-check codes: Part 2 - Efficient coding architectures
IEEE Solid-State Circuits Magazine, Vol. 9, Núm. 1, pp. 23-28
2016
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Algorithms and VLSI Architectures for Low-Density Parity-Check Codes: Part 1-Low-Complexity Iterative Decoding
IEEE Solid-State Circuits Magazine, Vol. 8, Núm. 4, pp. 57-63
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High-Performance NB-LDPC Decoder With Reduction of Message Exchange
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 5, pp. 1950-1961
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Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 8, pp. 2643-2653
2015
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A 630 Mbps non-binary LDPC decoder for FPGA
Proceedings - IEEE International Symposium on Circuits and Systems
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One minimum only trellis decoder for non-binary low-density parity-check codes
IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, Núm. 1, pp. 177-184
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Reduction of Complexity for Nonbinary LDPC Decoders with Compressed Messages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 11, pp. 2676-2679
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Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 9, pp. 1783-1792
2014
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A symbol flipping decoder for NB-LDPC relying on multiple votes
International Symposium on Turbo Codes and Iterative Information Processing, ISTC
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Multiple-vote symbol-flipping decoder for nonbinary LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 11, pp. 2256-2267