Publicacións en colaboración con investigadores/as de Tianjin University (7)

2018

  1. A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

    IEEE Transactions on Computers, Vol. 67, Núm. 7, pp. 1039-1045

  2. An efficient fault-tolerance design for integer parallel matrix-vector multiplications

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, Núm. 1, pp. 211-215

  3. Efficient Fault-Tolerant Design for Parallel Matched Filters

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, Núm. 3, pp. 366-370

2016

  1. A novel concurrent error detection technique for the fast Fourier transform implemented in SRAM-based FPGAs

    Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

  2. Efficient fault tolerant parallel matrix-vector multiplications

    2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016

  3. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 2, pp. 769-773

2015

  1. Efficient Coding Schemes for Fault-Tolerant Parallel Filters

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 62, Núm. 7, pp. 666-670