Publicaciones en las que colabora con DANIEL ÁNGEL CHAVER MARTÍNEZ (28)

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2017

  1. Towards completely fair scheduling on asymmetric single-ISA multicore processors

    Journal of Parallel and Distributed Computing, Vol. 102, pp. 115-131

2016

  1. OpenIRS-UCM: An Integral Solution for Interactive Response Systems

    International Journal of Engineering Education, Vol. 32, Núm. 2, pp. 873-885

2015

  1. ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems

    Proceedings of the ACM Symposium on Applied Computing

  2. An OS-Oriented performance monitoring tool for multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2014

  1. Exploring the throughput-fairness trade-off on asymmetric multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2013

  1. Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling

    Performance Evaluation Review

2012

  1. OpenIRS-UCM: An open-source multi-platform for interactive response systems

    Annual Conference on Innovation and Technology in Computer Science Education, ITiCSE

2011

  1. Hybrid timing-address oriented load-store queue filtering for an x86 architecture

    IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Energy reduction of the fetch mechanism through dynamic adaptation

    IET Computers and Digital Techniques, Vol. 2, Núm. 2, pp. 94-107

  2. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398

  3. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    Proceedings of the International Symposium on Low Power Electronics and Design

2005

  1. A Per-Module adaptive fetch mechanism

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  2. A power-efficient and scalable load-store queue design

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Energy-aware fetch mechanism: Trace cache and BTB customization

    Proceedings of the International Symposium on Low Power Electronics and Design

  4. Gestión eficiente de la LSQ basada en mecanismos de filtrado

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]