Publikationen, an denen er mitarbeitet Javier Valls (27)

2024

  1. Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes

    Quantum, Vol. 8

2023

  1. Layered Decoding of Quantum LDPC Codes

    2023 12th International Symposium on Topics in Coding, ISTC 2023

  2. Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures

    EPJ Quantum Technology, Vol. 10, Núm. 1

2019

  1. A test vector generation method based on symbol error probabilities for low-complexity chase soft-decision reed-solomon decoding

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Núm. 6, pp. 2198-2207

  2. Reed–Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems

    Circuits, Systems, and Signal Processing, Vol. 38, Núm. 4, pp. 1793-1810

  3. Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes

    Circuits, Systems, and Signal Processing, Vol. 38, Núm. 11, pp. 5068-5080

  4. Soft-decision low-complexity chase decoders for the RS(255,239) code

    Electronics (Switzerland), Vol. 8, Núm. 1

2018

  1. High-throughput one-channel RS(255,239) Decoder

    Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018

  2. Soft-decision LCC Decoder Architecture with η=4 for RS(255,239)

    2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018

2016

  1. High-Performance NB-LDPC Decoder With Reduction of Message Exchange

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 5, pp. 1950-1961

  2. Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 8, pp. 2643-2653

2015

  1. A 630 Mbps non-binary LDPC decoder for FPGA

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. One minimum only trellis decoder for non-binary low-density parity-check codes

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, Núm. 1, pp. 177-184

  3. Reduction of Complexity for Nonbinary LDPC Decoders with Compressed Messages

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 11, pp. 2676-2679

  4. Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 9, pp. 1783-1792

2014

  1. A symbol flipping decoder for NB-LDPC relying on multiple votes

    International Symposium on Turbo Codes and Iterative Information Processing, ISTC

  2. Multiple-vote symbol-flipping decoder for nonbinary LDPC codes

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 11, pp. 2256-2267

  3. Non-Binary LDPC decoder based on symbol flipping with multiple votes

    IEEE Communications Letters, Vol. 18, Núm. 5, pp. 749-752

  4. Nonbinary LDPC decoder based on simplified enhanced generalized bit-flipping algorithm

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1455-1459

  5. Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree

    IEEE Communications Letters, Vol. 18, Núm. 12, pp. 2065-2068