Publicaciones en colaboración con investigadores/as de Universidad de Los Andes (Venezuela) (7)

2016

  1. High-Performance NB-LDPC Decoder With Reduction of Message Exchange

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 5, pp. 1950-1961

  2. Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 8, pp. 2643-2653

2015

  1. A 630 Mbps non-binary LDPC decoder for FPGA

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. One minimum only trellis decoder for non-binary low-density parity-check codes

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, Núm. 1, pp. 177-184

  3. Reduction of Complexity for Nonbinary LDPC Decoders with Compressed Messages

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 11, pp. 2676-2679

  4. Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Núm. 9, pp. 1783-1792

2013

  1. Low latency T-EMS decoder for non-binary LDPC codes

    Conference Record - Asilomar Conference on Signals, Systems and Computers